In the wave of technological evolution, energy technology has gradually become the core driving force for the development of modern industries. From mobile devices to cloud servers, from electric vehicles to smart cities, technology products increasingly emphasize the balance between efficiency, speed, and sustainable energy, all of which require more efficient and stable power conversion technologies.

With the increasing demand for energy efficiency and power density in various applications, traditional power components based on silicon (Si) are facing extreme physical and performance challenges. This has also prompted the industry to seek more promising new materials, among which Gallium Nitride (GaN) is undoubtedly one of the most representative technologies. This article will introduce the advantages of GaN technology, an overview of ON Semiconductor iGaN, VDD, LDO bypass capacitors, and more.

Advantages of GaN technology

GaN, as a wide bandgap semiconductor, naturally outperforms silicon in material properties and has significant advantages in multiple key indicators. Under the same output power conditions, GaN can operate at MHz level switching frequencies, significantly reducing the volume of magnetic components (such as transformers and inductors) and filtering capacitors, achieving higher power density and smaller system size.

GaN components have small input and output capacitors, as well as no reverse recovery current, which can effectively reduce Dead Time Loss and Reverse Recovery Loss, allowing them to maintain high efficiency even under high-frequency switching. Although GaN has a higher unit area cost than silicon, its lower RDS (on) results in better overall efficiency and reduces heat sink area and system heat dissipation requirements.

Although GaN itself has excellent performance, its driving and control difficulties are relatively high. The design challenges brought by simply using discrete GaN cannot be ignored, especially in high-frequency driving, PCB wiring, EMI control, and reliability design, which are much more difficult than traditional silicon MOSFETs. In order to solve the above problems, Integrated GaN (iGaN) technology has emerged.

Anson Mei iGaN Overview

This article will introduce the iGaN product launched by onsemi, providing readers with practical references in component selection and system design. At the same time, this article focuses on practical skills and reference design criteria for PCB Layout, assisting designers in applying and optimizing system performance in practice. At the end of the article, provide a reference design and experimental data for a 300W high-performance game adapter.

Ansenmei integrates e-mode GaN and gate driver into a single package. This integration significantly reduces the wiring length and related parasitic parameters on the PCB, allowing GaN switches to operate faster and more stably. As shown in Figure 1, the advantages brought by Ansenmei's products include:

·PWM signal amplitude compliance: It is compatible with multiple PWM signal amplitudes, including 3.3V, 5V, and 10V. This makes integrated GaN technology more flexible and adaptable in different application scenarios. However, discrete GaN cannot meet the requirements of various PWM signal amplitudes.

·6V clamp driving protection for GaN gate oxide layer: With 6V clamp driving function, it can effectively protect the GaN gate oxide layer and prevent it from being damaged by high voltage. The discrete GaN technology lacks this protective measure, which may cause damage to the GaN gate oxide layer in high voltage environments.

·Adjusting VDRV and driving intensity to drive GaN speed: The driving intensity can be adjusted according to different application requirements. This makes iGaN technology more flexible and adaptable in different application scenarios.

·Minimizing the line inductance between the driver and GaN: This can help improve the performance and reliability of the system by minimizing the line inductance between the driver and GaN. Discrete GaN technology cannot effectively reduce line inductance, which may lead to a decrease in system performance.

·Noise immunity/CMTI rating (150+V/ns): It has high noise immunity and CMTI rating (150+V/ns), which helps improve the stability and reliability of the system. Discrete GaN technology cannot provide this function, which may lead to system instability in high noise environments.

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Figure 1 Advantages of Ansenmei iGaN

As a leading iGaN technology supplier in the industry, Ansenmei's NCP5892x series covers the range of 650V/50mohm, 78mohm, and 150mohm, and is widely used in fast charging power supplies, industrial power supplies, server power modules, and other fields.

Figure 2 presents the functional block diagram and pin description using NCP58921 as an example. This product integrates high-performance high-frequency drivers and 650 V, 50 m Ω gallium nitride (GaN) into a switch structure. The powerful combination of silicon drivers and GaN HEMT power switches provides superior performance compared to discrete GaN. At the same time, the TQFN26 8 x 8 mm package reduces circuit and package parasitic effects, while achieving a more compact design.

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Figure 2 Functional Block Diagram and Pin Description of NCP58921

On the other hand, users will check the voltage stress of components or the EMI characteristics of the system under given applications and conditions. The reason is that PCB layout parasitic capacitance, inductance parasitic capacitance, and power circuit stray inductance can affect the performance of switch switching. NCP58921 can adjust the turn-on slew rate (dv/dt) by connecting a series RON resistor and a VDR decoupling CVDR capacitor.

The recommended VDR decoupling capacitor is a multi-layer ceramic capacitor (MLCC) X7R material. The CVDR capacitor has a capacitance of 100 nF and a rated voltage higher than 25 V, providing better thermal/voltage stability. Be sure to add a series resistor (RON) in order to set the turn on sleep rate and perform application debugging. The recommended starting RON value is 33 Ω. The RON resistance value depends on the application requirements and operating frequency, but 100 Ω should be considered as the maximum value. Figure 3 shows different dv/dt values after adjusting different RON values.

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Figure 3: iGaN generates different dv/dt by adjusting RON

Although iGaN has significantly reduced the difficulties in driving and matching traditional GaN designs, a good PCB layout is still the key to leveraging its high-speed and high-efficiency characteristics. Especially in high voltage, high frequency, and high power density applications, even minor wiring errors can cause EMI, switching spikes, oscillations, and even component damage.

Next, guided by practical design, the PCB routing principles of iGaN will be gradually explained, covering key component placement, high-frequency circuit design, and grounding treatment.

VDD, LDO bypass capacitor

IGaN requires higher current during the brief charging period of the gate capacitor during high-speed driving process. This power supply current is provided through an internal regulator from the VDD decoupling capacitor CVDD, which is used to decouple the VDD power supply voltage. CVDD must be directly connected between the VDD and GND pins. The CVDD capacitor should be a ceramic capacitor with at least 1 uF and should be located as close as possible to the power pin to filter out all spikes under high-frequency operation.

LDO OUT is the output of a universal voltage regulator used to power 5V digital isolators or isolated gate drivers. This voltage regulator requires a ceramic capacitor to be connected between the LDO OUT and GND pins to decouple the output voltage. The recommended capacitance value is 100 nF, and the material should be X7R with good stability. Figure 4 shows a typical half bridge circuit PCB layout and component positions. It can be seen that CVDD is located near the VDD pin, and there is also a ceramic capacitor between the LDO OUT pin and GND.

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Figure 4 Layout layout under half bridge architecture

Reduce parasitic inductance

If the parasitic inductance in the power circuit is too large, coupled with the extremely high current change rate di/dt of iGaN, it is easy to generate spike voltage and even cause damage. At the same time, this will also generate a large amount of radiated EMI. As shown in Figure 5, Vbus, HB, GND, and the bypass ceramic capacitor next to them are marked. We can see that the entire high-power current loop starts from Vbus → iGaN → Switch Node → iGaN, and then returns to GND via Via. In order to reduce parasitic inductance, iGaN and bypass capacitors (MLCC) are placed in close proximity to each other during PCB layout, reducing the length of the circuit. At the same time, using a wide copper surface and having a complete GND as the return path in the next layer can create a cancellation of electric and magnetic fields. The thinner the plate thickness between the upper and inner layers, the better, which helps to form coupling inductance to effectively reduce parasitic inductance along the entire path.

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Figure 5 High power current path under half bridge architecture

Reduce parasitic capacitance of switch nodes

IGaN devices have very low output capacitance and switch quickly at high dv/dt, resulting in very low switching losses. To maintain this low switching loss, it is necessary to minimize the additional capacitance added to the switch node. According to the formula for capacitance, C=0.0886? εr? A/h

here:

ε r: is the dielectric constant of the material, and FR4 material has a dielectric constant of approximately 4.5

A: The overlap area between the Switch Node and other planes (such as GND or Heatsink)

h: It is the distance between these two conductors (usually plate thickness, dielectric)

Simply put, minimizing the overlap between the switch node plane and other power and ground planes will result in a decrease in the overall parasitic capacitance C. In addition, the following guidelines can also be used to minimize the parasitic capacitance of switch nodes:

1. Place the power inductor as close as possible to the iGaN device.

2. Power inductors must be constructed with a single-layer winding to minimize the capacitance inside the winding.

If a single-layer inductor is not feasible, consider placing a small inductor between the main inductor and the iGaN device to effectively shield GaN from the influence of additional capacitance.

If using a back heat sink, use the minimum copper coverage area of the switch nodes on the bottom copper layer to improve heat dissipation.

This is reported by Top Components, a leading supplier of electronic components in the semiconductor industry

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Name: John Chen

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