Cadence launches industry's first LPDDR6/5X 14.4Gbps memory IP, empowering the next generation of AI infrastructure

The integrated subsystem has been optimized for customer applications, including chiplets

Shanghai, China, July 16, 2025- Cadence Electronics (NASDAQ: CDNS) recently announced that the industry's first LPDDR6/5X memory IP system solution has been successfully taped out. This solution has been optimized with a running speed of up to 14.4Gbps, which is 50% faster than the previous generation LPDDR DRAM. The new Cadence LPDDR6/5X memory IP system solution is a key driver for expanding AI infrastructure. After expansion, the AI infrastructure can adapt to the memory bandwidth and capacity requirements of the new generation of AI LLM, proxy AI, and other vertical computing intensive workloads. In this regard, Cadence is currently collaborating with leading AI, high-performance computing (HPC), and data center clients on multiple fronts.

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Cadence LPDDR6/5X system solution example

Cadence's IP that meets the JEDEC LPDDR6/5X standard includes advanced PHY architecture and high-performance controllers designed to maximize power, performance, and area (PPA) while supporting LPDDR6 and LPDDR5X DRAM protocols for greater flexibility. This solution utilizes the Cadence Chiplet framework to support native integration into traditional single-chip SoC and multi chip system architectures, thereby achieving heterogeneous Chiplet integration. The Chiplet framework, which includes the previous generation LPDDR, has been successfully taped out in 2024.

Boyd Phelps, Senior Vice President and General Manager of the Chip Solutions Division at Cadence, stated that the evolution of data centers from HPC computing virtualization to large-scale AI training and inference has driven the large-scale construction of AI infrastructure. In this context, it is necessary to consider how to achieve efficient data movement through memory interfaces. LPDDR6 has become a key driving factor in accelerating computing, providing the speed, bandwidth, power configuration, and capacity required for efficient execution of AI inference. With this tape out, Cadence will continue to maintain our outstanding position in the memory IP field, providing the industry's first LPDDR6 solution delivered in the form of an integrated subsystem, optimized for customer applications. ”

The complete PHY and controller memory system adopts a new high-performance, scalable, and adaptable architecture based on Cadence's proven and successful DDR5 12.8Gbps, LPDDR5X 10.7Gbps, and GDDR7-36G product lines. As the first product in Cadence's new LPDDR6 IP product line, it supports LPDDR6 and LPDDR5X standards, including LPDDR5X CAMM2.

This advanced LPDDR6/5X memory IP system solution is suitable for the AI, mobile, consumer electronics, enterprise HPC, and cloud data center markets, providing greater flexibility for end products with various performance, capacity, and cost goals, ensuring long-term production operations. LPDDR6/5X PHY can be customized for different packages and system topologies, and can be provided as a plug-in hard core. This ensures fast and reliable integration, which means speeding up the time to market.

The Cadence LPDDR6/5X controller includes a complete set of industry standards and advanced memory interface features, such as support for Arm AMBA AXI bus. The memory controller is provided as an RTL soft core to provide greater flexibility in terms of functionality, power consumption, area, and performance.

The Cadence LPDDR6 solution includes an LPDDR6 memory model that allows engineers to perform comprehensive validation and ensure system on chip (SoC) design is compatible with the latest JEDEC interface standards, helping them adopt this new technology as soon as possible. The LPDDR6 memory model includes a complete protocol check, functional coverage, and verification plan.

The new LPDDR6/5X IP is the latest member of Cadence's comprehensive memory IP system solution series, which also includes DDR, GDDR, and HBM. Cadence memory IP is designed using the company's excellent analog/mixed signal design tools. When used in conjunction with Cadence's UCIeTM based Chiplet framework, the new LPDDR6/5X IP and Cadence's other advanced memory and interface IPs provide an optimized solution that supports fast Chiplet implementation.

For more information about the new LPDDR6/5X IP, please visit the LPDDR product page on cadence.com.

About Cadence

Cadence is a market leader in the fields of AI and digital twins, pioneering the use of computing software to accelerate engineering design innovation from silicon wafers to systems. Our design solution is based on Cadence's Intelligent System DesignTM strategy, which can help leading semiconductor and systems companies around the world build next-generation products (from chips to fully electromechanical systems), serving fields such as ultra large scale computing, mobile communications, automotive, aerospace, industry, life sciences, and robotics. In 2024, Cadence was selected by The Wall Street Journal as one of the "Top 100 Best Management Companies in the World". Cadence solutions offer unlimited opportunities. For more information, please visit the company website www.cadence.com

2025 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, the Cadence logo, and other Cadence logos listed on www.cadence.com/go/trademarks are trademarks or registered trademarks of Cadence Design Systems, Inc. Arm and AMBA are registered trademarks of Arm Limited (or its subsidiaries) in the United States and/or other regions. UCIe is a trademark of UCIe Consortium. All other identifiers are assets of their respective owners.

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