With the rapid development of technology, the demand for high-temperature resistant integrated circuits (ICs) in commercial, industrial, and automotive fields continues to rise?. The high temperature environment will seriously restrict the performance, reliability, and safety of integrated circuits, and it is urgent to overcome relevant technical difficulties through innovative technological means?. This article aims to explore the impact of high temperatures on integrated circuits, introduce the challenges brought by high junction temperatures, and provide design techniques suitable for high power to address these challenges.

Challenges brought by high junction temperature

Semiconductor devices operating at higher temperatures can reduce circuit performance and shorten their lifespan. For silicon-based semiconductors, transistor parameters will decrease with increasing temperature, and due to the influence of intrinsic carrier density, the maximum limit will be below 300 ℃. Devices relying on selective doping may fail or exhibit poor performance.

The main technical challenges that affect the operation of ICs at high temperatures include:

Leakage current increases

The threshold voltage of MOS transistors decreases

Reduced carrier mobility

Enhance the sensitivity of latch up effect (Latch Up)

Accelerated loss mechanism

Challenges to packaging and bonding reliability

Understanding the challenges faced at high temperatures is crucial in designing ICs that can operate at high temperatures. The following text will explore the challenges faced by IC design.

1. Increased leakage current

The increase in leakage current in CMOS circuits is mainly caused by the increase in semiconductor PN junction leakage and subthreshold channel leakage.

Reverse biased PN junction leakage

At higher temperatures, the increase in thermal energy in semiconductors leads to the generation of more electron hole pairs, resulting in higher leakage currents. Leakage depends on the doping level and usually increases exponentially with temperature. According to widely used empirical rules, for every 10 ℃ increase in temperature, the junction current approximately doubles.

The leakage current of a diode is composed of drift current and diffusion current:

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Among them, q is the basic charge of the electron, Aj is the junction area, ni is the intrinsic carrier concentration, W is the depletion region width, τ is the effective minority carrier lifetime, L is the diffusion length, and N is the neutral region doping density.

At moderate temperatures, leakage current is mainly caused by the heat generated by electron hole pairs in the depletion region. At high temperatures, leakage current is mainly caused by minority carriers generated in the neutral region. The drift current is proportional to the depletion region width, which means it is proportional to the square root of the junction voltage (under normal reverse voltage), while the diffusion current is independent of the junction voltage and inversely proportional to the doping density N. The higher the doping level, the less diffusion leakage occurs at temperatures above about 150 ° C.

The exponential increase in leakage current affects most active devices (such as bipolar transistors, MOS transistors, diodes) and some passive devices (such as diffusion capacitors, resistors). However, devices isolated by oxides, such as polysilicon resistors, polysilicon diodes, plot poly capacitors, and metal metal capacitors, are not affected by junction leakage. Junction leakage is considered the most severe challenge in high-temperature bulk CMOS circuits.

Subthreshold channel leakage

When a MOS transistor is turned off, the gate source voltage VGS is usually set to zero. Due to the non-zero drain to source voltage VDS, there will be a small current flowing between the drain and source. When Vgs is below the threshold voltage Vt, i.e. in the subthreshold or weak inversion region, subthreshold leakage occurs. The drain source current in this region is not zero, but exponentially related to Vgs, mainly due to the diffusion of minority carriers.

The current largely depends on temperature, process, transistor size, and type. The current of short channel transistors will increase, while the current of transistors with higher threshold voltages will decrease. The subthreshold slope factor S describes the effectiveness of switching a transistor from off (low current) to on (high current), defined as the amount of change in VGS required to make the drain current change tenfold:

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Among them, n is the sub threshold slope coefficient (usually around 1.5). For n=1, the slope factor is 60mV/10 times, which means that for every 60mV below the threshold voltage Vt, the drain current will decrease tenfold. A typical n=1.5 means that the current drops slowly, at 90mV/10 times. In order to effectively shut down MOS transistors and reduce subthreshold leakage, the gate voltage must be lowered to a level sufficiently below the threshold voltage.

Gate oxide tunneling leakage

For extremely thin gate oxide layers (thickness less than about 3 nanometers), the influence of tunneling leakage current must be considered. This current is temperature dependent and triggered by multiple mechanisms. Fowler Nordheim tunneling occurs when electrons pass through a triangular potential barrier formed by an oxide layer under the action of a high electric field. As the effective barrier height decreases, the tunnel current increases with temperature. Higher temperatures also enhance trap assisted tunneling, where electrons pass through intermediate trap states in the oxide layer. For ultra-thin oxide layers, direct tunneling becomes significant, and due to the increase in electron thermal energy, the probability of tunneling also increases.

2. Decrease in threshold voltage

The threshold voltage Vt of MOS transistors is closely related to temperature and usually decreases linearly with increasing temperature. This is due to factors such as an increase in intrinsic carrier concentration, narrowing of the semiconductor bandgap, changes in surface potential at the semiconductor oxide interface, and a decrease in carrier mobility. The decrease in threshold voltage caused by temperature rise will lead to an exponential increase in subthreshold leakage current.

3. Decrease in carrier mobility

The carrier mobility directly affects the performance of MOS transistors, which is affected by lattice scattering and impurity scattering. As the temperature increases, lattice vibrations (phonons) intensify, leading to more frequent scattering of charge carriers and a decrease in mobility. In addition, high temperatures can increase the intrinsic carrier concentration, causing more carrier carrier scattering and further reducing mobility. When the temperature rises from 25 ° C to 200 ° C, the carrier mobility is approximately halved.

The carrier mobility significantly affects multiple key MOS parameters. The decrease in carrier mobility will reduce the driving current, decrease the switching speed and overall performance of the transistor. Higher on resistance will increase power loss and reduce efficiency. Lower mobility also reduces transconductance, slows down subthreshold slope (increasing subthreshold leakage), lowers carrier saturation velocity (crucial for short channel devices), and indirectly affects threshold voltage.

4. Improve the sensitivity of latch up effect

The isolation between diodes, transistors, and other components in integrated circuits is achieved through reverse biased P-N junctions. In the process of circuit development, preventive measures need to be taken to ensure that these junctions always reliably block under expected application conditions. These P-N junctions form N-P-N and P-N-P structures with other adjacent junctions, resulting in parasitic NPN or PNP transistors that may be accidentally activated.

When parasitic PNP and NPN bipolar transistors interact to form a low impedance path between the power rail and ground, latch up effect occurs in CMOS ICs. This will form a thyristor rectifier (SCR) with positive feedback, causing excessive current flow and potentially causing permanent device damage. Figure 1 shows a cross-sectional layout of a standard CMOS inverter. The figure also includes parasitic NPN and PNP transistors. During normal operation, all junctions are reverse biased.

The activation of the latch up effect mainly depends on the beta values of parasitic NPN and PNP transistors, as well as the N-well, P-well, and substrate resistance. As the temperature increases, the DC current gain (β) of bipolar transistors and the resistance of the well and substrate also increase.

Under high temperature conditions, the increase in sensitivity of the latch up effect can also be seen as a decrease in the threshold voltage of bipolar junction transistors (BJTs), making it easier to generate voltage drops sufficient to activate parasitic bipolar transistors on the well and substrate resistance. The magnitude of the decrease in base emitter voltage with temperature variation is about -2mV/℃. When the temperature rises from 25 ℃ to 200 ℃, the base emitter voltage decreases by 350mV. The typical threshold voltage at room temperature is 0.7V, which means that the threshold voltage is approximately halved.

5. Accelerated loss mechanism

The Arrhenius law is widely used in reliability engineering to simulate the effect of temperature on the failure rate of materials and components.

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Among them, R (T) is the rate constant, Ea is the activation energy, k is the Boltzmann constant (8.617 · 10-5eV/K), and T is the absolute temperature (unit: Kelvin). Usually, for every 10 ° C increase, reliability decreases by half.

Time lapse TDDB

TDDB is a failure mechanism in electronic devices, in which dielectric materials (such as the gate oxide layer in MOS transistors) degrade over time due to prolonged exposure to an electric field, leading to an increase in leakage current. When voltage promotes the flow of high-energy electrons, conductive paths are formed inside the oxide layer, while traps and defects are generated. When these conductive paths cause a short circuit in the oxide layer, the dielectric layer will fail. The failure time TF decreases exponentially with increasing temperature.

Negative/Positive Bias Temperature Instability - NBTI/PBTI

NBTI affects p-channel MOS devices operating with negative gate source voltage, while PBTI affects NMOS transistors located in the accumulation region. Under gate bias, defects and traps increase, leading to an increase in threshold voltage and a decrease in drain current and transconductance. This degradation exhibits logarithmic time dependence and exponential temperature rise, with partial recovery above 125 ° C.

electromigration

Electromigration refers to the gradual displacement of metal atoms in a conductor due to the flow of current, resulting in the formation of voids and small bumps. Therefore, if the gap formed in the metal wire is large enough to cut the metal wire, it will lead to an open circuit; If these protrusions extend long enough to form a bridge between the affected metal and an adjacent metal, it may lead to a short circuit. Electromigration accelerates with the increase of current density and temperature, especially after the formation of voids, which can lead to current crowding and local heating. The probability of metal wire failure is exponentially related to temperature, square related to current density, and linearly related to wire length. Copper interconnect devices can withstand a current density about five times that of aluminum, while maintaining similar reliability.

hot carrier degradation

When channel electrons accelerate in a high electric field near the drain of a MOS transistor, thermal carrier degradation occurs. Generate interface states, traps, or holes in the gate oxide layer. It affects parameters such as threshold voltage VT, current gain β, on resistance RD-SON, and sub threshold leakage. At higher temperatures, the average free path decreases, reducing the energy obtained by charge carriers and making the degradation of hot charge carriers more significant at lower temperatures.

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