Onsemi cascode FET (silicon carbide common source common gate field-effect transistor) has many advantages in both hard switching and soft switching applications. This article will focus on introducing the Cascode structure.

Introduction to Cascode

Silicon carbide junction field-effect transistors (SiC JFETs) have some significant advantages over other competing technologies, especially in terms of low on resistance (known as RDS. A) given the chip area. In order to achieve the lowest RDS. A trade-off is its normally open characteristic, which means that if there is no gate source voltage or the gate of the JFET is in a floating state, the JFET will be fully conductive.

However, switch mode typically requires a normally off state in applications. Therefore, by combining SiC JFET with low-voltage silicon MOSFET in cascode configuration, a normally off switch mode "FET" is constructed, which retains most of the advantages of SiC JFET.

Cascode structure

The Cascode structure is formed by connecting a SiC JFET in series with a low voltage, normally off silicon (Si) MOSFET, where the gate of the JFET is connected to the source of the MOSFET. The drain source voltage of MOSFET is the inverse of the gate source voltage of JFET, which gives the cascode structure a common normally off characteristic. This structure can block current within the rated leakage source voltage range, but like any MOSFET (whether silicon-based or silicon carbide based device), its reverse current can always flow.

When the internal MOSFET is conducting or a reverse current flows, regardless of the gate voltage of the cascode, the gate source voltage of the JFET is almost zero, and the JFET is in a conducting state. When the MOSFET is turned off and there is a positive VDS (drain source voltage) across the cascode, the VDS of the MOSFET will increase, while the gate source voltage of the JFET will decrease below the threshold voltage of the JFET, thereby turning off the JFET. Please refer to Figure 1.

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Figure 2: Discrete cascode Structure

The discrete cascode structure adopts parallel chips, as shown in Figure 2 (a), or stacked chips, as shown in Figure 2 (b). In both cases, SiC JFETs are typically silver sintered on the packaging lead frame.

In a side-by-side configuration, the MOSFET is mounted on a metal coated ceramic isolator with two sets of source connection lines: one set connects the JFET source and MOSFET drain (on the top surface of the metal coated ceramic), and the other set connects the MOSFET source and source pins. In the stacked chip configuration, the connection line between the JFET source and MOSFET drain is eliminated, thereby reducing stray inductance. And use smaller diameter connecting wires to connect the gate of JFET and MOSFET.

This MOSFET is designed specifically for cascode structures, with an active avalanche voltage set at approximately 25V. The MOSFET is manufactured using a 30V silicon process and has a low on resistance RDS (on), typically only 10% of that of JFETs, as well as low reverse recovery charge QRR and other characteristics. JFET is used to block high voltage. Most of the switching and conduction losses are concentrated on JFETs.

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Figure 3: Forward and Reverse Current Operation of Cascode

The conduction resistance RDS (on) of Cascode includes the conduction resistance of SiC JFET and low-voltage Si MOSFET. When the cascode gate is turned off, reverse current flows through the MOSFET body diode, automatically turning on the JFET, as shown in the asynchronous reverse current situation in Figure 3 (b).

In this case, the source drain voltage is the voltage drop of the MOSFET body diode plus the voltage drop of the JFET on resistance. Due to the fact that MOSFETs within the cascode are made of silicon, the source drain voltage when the gate is turned off is less than half of that of similar SiC MOSFETs. When the gate is conductive, the cascode structure has the same conduction loss under forward and reverse currents.

The gate voltage range of Cascode is very flexible for two reasons. Firstly, the gate is a MOSFET gate, which has a threshold voltage close to 5V at room temperature and does not require a negative gate voltage. The gate voltage range is ± 20 V, and there is no risk of threshold voltage drift or hysteresis. At the same time, a gate protection Zener diode is built-in. Secondly, cascode has high gain. Figure 4 shows the output characteristic curve of the cascode UJ4SC075005L8S with a 4th generation stacked chip structure using TOLL (MO-229) packaging at 25 ° C.

Figure 4: Cascode's high gain can achieve 10V gate drive

Please note that when the cascode gate source voltage exceeds about 8V, the change in its conductivity is very small. Once the MOSFET is turned on, the JFET is fully conductive. This means that the cascode can be driven with a bootstrap voltage of 0 to 10 V, thereby minimizing the power and cost of the gate driver. On the other hand, a wider range of gate voltages (such as -5 to+18 V) will not cause damage to the device.

This means that during the switching voltage conversion process, the dVDS/dt of cascode is mainly determined by external circuits rather than cascode gate resistance. The switching speed of Cascode's MOSFET can be adjusted through its gate resistance, while the switching speed of JFET is partially determined by MOSFET and partially determined by external circuits. This explains why in the case of hard switching, the cascode structure requires the use of a drain source buffer circuit (SNR) to control the turn off speed and suppress voltage overshoot, which will be explained in the following text. All JFET output capacitors (including gate drain capacitors and drain source capacitors) are gate drain capacitors. The output capacitance Coss of cascode is approximately equal to the gate drain capacitance of JFET. The input capacitance Ciss of cascode mainly comes from the MOSFET gate source capacitance of cascode.

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